Wafer fabrication: 300mm wafer fabrication line simulation model

  • Authors:
  • Sameer T. Shikalgar;David Fronckowiak;Edward A. MacNair

  • Affiliations:
  • IBM Microelectronics Division, East Fishkill, NY;IBM Microelectronics Division, East Fishkill, NY;IBM T. J. Watson Research Center, Yorktown Heights, NY

  • Venue:
  • Proceedings of the 34th conference on Winter simulation: exploring new frontiers
  • Year:
  • 2002

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Abstract

The importance of semiconductor wafer fabrication has been increasing steadily over the past decade. Wafer fabrication is the most technologically complex and capital intensive phase in semiconductor manufacturing. It involves the processing of wafers of silicon in order to build up layers and patterns of metal and wafer material. Many operations have to be performed in a clean room environment to prevent particulate contamination of wafers. Also, since the machines on which the wafers are processed are expensive, service contention is an important concern. All these factors underline the importance of seeking policies to design and operate them efficiently. We describe a simulation model of a planned 300mm wafer fabrication line that we are using to make strategic decisions related to the factory.