Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays

Authors:
Gustavo Pereira;Antonio Andrade Jr.;Tiago R. Balen;Marcelo Lubaszewski;Florence Azais;Michel Renovell
Affiliations:
University Federal do Rio Grande do Sul;University Federal do Rio Grande do Sul;University Federal do Rio Grande do Sul;Universidad Federal do Rio Grande do Sul and Universidad de Sevilla;Université de Montpellier II;Université de Montpellier II
Venue:
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Year:
2005

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Abstract

The test of Field Programmable Analog Arrays (FPAA) may be performed based on partitioning these devices in three main parts: I/O cells, interconnection networks and configurable analog blocks. In this work, a scheme for testing the I/O cells and the local and global interconnection networks of FPAAs is proposed, using an adjacency graph model to represent the programmable interconnection and I/O resources, and then devising a set of test configurations (TC) by solving graph coloring problems. The goal is to achieve a near minimum number of TCs ensuring all stuck-open and stuck-on faults in switches, as well as opens and shorts in wires, are covered. Large parametric faults in interconnects are implicitly covered in these TCs by judiciously choosing test stimuli and, in I/O buffers, by means of an Oscillation-based Test Strategy.