Embedded Software-Based Self-Test for Programmable Core-Based Designs
IEEE Design & Test
An Approach to the Built-In Self-Test of Field Programmable Analog Arrays
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Applying the Oscillation Test Strategy to FPAA's Configurable Analog Blocks
Journal of Electronic Testing: Theory and Applications
Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
TESTING THE CONFIGURABLE ANALOG BLOCKS OF FIELD PROGRAMMABLE ANALOG ARRAYS
ITC '04 Proceedings of the International Test Conference on International Test Conference
On-line Testing Field Programmable Analog Array Circuits
ITC '04 Proceedings of the International Test Conference on International Test Conference
Functional Test of Field Programmable Analog Arrays
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Integrated Circuit Test Engineering: Modern Techniques
Integrated Circuit Test Engineering: Modern Techniques
Built-In Self-Test of Field Programmable Analog Arrays based on Transient Response Analysis
Journal of Electronic Testing: Theory and Applications
MSP430 Microcontroller Basics
Diagnosis of specification parametric faults in the FPAA: the RBF neural network approach
ECC'08 Proceedings of the 2nd conference on European computing conference
Analog testing by characteristic observation inference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper proposes a self-test strategy, analog configurability test (ACT), for an embedded analog configurable circuit (EACC) composed of operational amplifiers and interconnection resources that are present in the MSP430 microcontroller family from Texas Instruments^(R). The ACT strategy minimizes the cost in hardware overhead by employing only the hardware and software resources of the microcontroller. Our test proposal consists in programming a reduced set of available configurations for the EACC and testing its functionality by measuring only a few key parameters. The processor executes an embedded test routine that sequentially programs the configurations, acquires data from an ADC channel and performs required calculations. The test strategy is experimentally evaluated using a commercial hardware provided by the vendor. Our experimental results show very good repeatability, with errors below the expected.