Operation and modeling of the MOS transistor
Operation and modeling of the MOS transistor
Analysis and Reduction of Capacitive Coupling Noise in High-Speed VLSI Circuits
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Design Considerations for Low-Power Ultra Wideband Receivers
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
An analysis of high-frequency noise in RF active CMOS mixers
Analog Integrated Circuits and Signal Processing
Small-area CMOS RF distributed mixer using multi-port inductors
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A low-voltage high-linearity ultra-wideband down-conversion mixer in 0.18-µm CMOS technology
Microelectronics Journal
A 3-10 GHz, 14 bands CMOS frequency synthesizer with spurs reduction for MB-OFDM UWB system
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low Cost Time Efficient Multi-tone Test Signal Generation Using OFDM Technique
Journal of Electronic Testing: Theory and Applications
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This paper presents the design and analysis of a novel distributed CMOS mixer for ultrawide-band (UWB) receivers. To achieve the UWB RF frequency range required for the UWB communications, the proposed mixer incorporates artificial inductance-capicitance (LC) delay lines in radio frequency (RF), local oscillator (LO), and intermediate frequency signal paths, and single-balanced mixer cells that are distributed along these LC circuits. Closed-form analytical model for the conversion gain of the mixer is presented. Furthermore, a comprehensive noise analysis of the proposed distributed mixer is carried out, which includes calculation of the mixer noise figure (NF) and derivation of the optimum number of stages, n, minimizing the NF. The designed mixer is capable of covering the RF and LO frequencies over a wide range of frequencies from 3.1-8.72 GHz. A two-stage distributed mixer has been fabricated in a 0.18-µm CMOS process. Experiments show a conversion gain of more than 2.5 dB for the entire range of the frequencies. The dc power consumption is 10.4 mW.