Cache Array Architecture Optimization at Deep Submicron Technologies
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Proceedings of the 33rd annual international symposium on Computer Architecture
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Overlay as the key to drive wafer scale 3D integration
Microelectronic Engineering
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
Proceedings of the 34th annual international symposium on Computer architecture
Strategies for improving the parametric yield and profits of 3D ICs
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Parametric yield management for 3D ICs: Models and strategies for improvement
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
Design space exploration for 3-D cache
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A qualitative security analysis of a new class of 3-d integrated crypto co-processors
Cryptography and Security
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The advantages of 3D design can be exploited by reducing the memoryaccess time. In this article, the authors use a simulator based on analyticalmodels to build an optimal processor-memory configuration for two designs:a graphics processor and a microprocessor.