Asynchronous Sigma-Delta analog-to digital converter based on the charge pump integrator
Analog Integrated Circuits and Signal Processing
An adaptive resolution computationally efficient short-time Fourier transform
Research Letters in Signal Processing
Adaptive reference levels in a level-crossing analog-to-digital converter
EURASIP Journal on Advances in Signal Processing
Analysis and simulation of continuous-time digital signal processors
Signal Processing
Adaptive rate sampling and filtering based on level crossing sampling
EURASIP Journal on Advances in Signal Processing
Designing asynchronous analog-to-digital converter with I2C interface
ETFA'09 Proceedings of the 14th IEEE international conference on Emerging technologies & factory automation
Event-driven data acquisition and digital signal processing: a tutorial
IEEE Transactions on Circuits and Systems II: Express Briefs
Tracking the best level set in a level-crossing analog-to-digital converter
Digital Signal Processing
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Distributed sensor networks, human body implants, and hand-held electronics have tight energy budgets that necessitate low power circuits. Most of these devices include an analog-to-digital converter (ADC) to process analog signals from the physical world. We describe a new topology for an asynchronous analog-to-digital converter, dubbed LCF-ADC, that has several major advantages over previously-designed ADCs, including reduced energy consumption and/or a simplification of the analog circuits required for its implementation. In this paper we describe the design of the LCF-ADC architecture, and present simulation results that show low power consumption. We discuss both theoretical considerations that determine the performance of our ADC as well as a proposed implementation. Comparisons with previously designed asynchronous analog-to-digital converters show the benefits of the LCF-ADC architecture. In 180 nm CMOS, our ADC is expected to consume 43 ìW at 160 kHz, and 438 ìW at 5 MHz.