IMPRES: integrated monitoring for processor reliability and security

  • Authors:

  • Roshan G. Ragel;Sri Parameswaran

  • Affiliations:

  • The University of New South Wales and National Information and Communications Technology Australia, Sydney NSW Australia;The University of New South Wales and National Information and Communications Technology Australia, Sydney NSW Australia

  • Venue:
  • Proceedings of the 43rd annual Design Automation Conference
  • Year:
  • 2006

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Abstract

Security and reliability in processor based systems are concernsrequiring adroit solutions.Securityis often compromised by code injection attacks, jeopardizing even `trusted software'.Reliabilityis of concern where unintended code is executed in modern processors with ever smaller feature sizes and low voltage swings causing bit flips. Countermeasures by software-only approaches increasecodesize by large amounts and therefore significantly reduce performance. Hardware assisted approaches add extensive amountsofhardware monitors and thus incur unacceptably highhardware cost. This paper presents a novel hardware/softwaretechniqueat the granularity of micro-instructions to reduce overheads considerably. Experiments show thatour technique incurs an additional hardware overhead of 0.91% and clock period increase of 0.06%. Average clock cycle and code size overheads are just 11.9% and 10.6% forfive industrystandard application benchmarks. These overheads are far smaller than have been previously encountered.