Hamming hypermeshes: high performance interconnection networks for pin-out limited systems

  • Authors:

  • Fernando Rodríguez-Salazar;John R. Barker

  • Affiliations:

  • Department of Electronics and Electrical Engineering, University of Glasgow, Glasgow, Scotland, United Kingdom;Department of Electronics and Electrical Engineering, University of Glasgow, Glasgow, Scotland, United Kingdom

  • Venue:
  • Performance Evaluation
  • Year:
  • 2006

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Abstract

Hypermeshes are promising candidates for the construction of high performance interconnection networks. Their main advantage is that they present a low diameter, high bandwidth, low latency network, which can naturally embed a wide range of communication patterns. Since a VLSI implementation of such a system is still far-off, we argue that any implementation is pin-out, rather than wire density limited. We will study the networks under this assumption. In this paper we introduce the Hamming hypermesh, which has a lower pin-out, in an attempt to enhance the performance of the network. It is shown both by theoretical work and simulations that this implementation outperforms previously proposed hypermeshes under the constant pin-out argument. Furthermore Hamming hypermeshes have the additional benefit of providing higher bandwidth channels and simpler switching structures. Since it has been shown that complete hypermeshes outperform the mesh, the torus, low dimensional k-ary n-cubes (with and without bypass channels), and multi-stage interconnection networks under the constant pin-out argument, it follows that incomplete hypermeshes outperform them as well.