PLDI '92 Proceedings of the ACM SIGPLAN 1992 conference on Programming language design and implementation
Register allocation via graph coloring
Register allocation via graph coloring
The multiflow trace scheduling compiler
The Journal of Supercomputing - Special issue on instruction-level parallelism
Improvements to graph coloring register allocation
ACM Transactions on Programming Languages and Systems (TOPLAS)
IEEE Transactions on Computers
URSA: A Unified ReSource Allocator for Registers and Functional Units in VLIW Architectures
PACT '93 Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism
Register Pressure Sensitive Redundancy Elimination
CC '99 Proceedings of the 8th International Conference on Compiler Construction, Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS'99
Optimization for the Intel® Itanium® architecture register stack
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Register allocation & spilling via graph coloring
SIGPLAN '82 Proceedings of the 1982 SIGPLAN symposium on Compiler construction
Value-driven redundancy elimination
Value-driven redundancy elimination
Region-based compilation
Compiler Optimizations for Transaction Processing Workloads on Itanium® Linux Systems
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
A Model-Based Framework: An Approach for Profit-Driven Optimization
Proceedings of the international symposium on Code generation and optimization
Reducing code size in VLIW instruction scheduling
Journal of Embedded Computing - Low-power Embedded Systems
Load scheduling: reducing pressure on distributed register files for free
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Techniques for Region-Based Register Allocation
Proceedings of the 7th annual IEEE/ACM International Symposium on Code Generation and Optimization
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Modern compiler transformations that eliminate redundant computations or reorder instructions, such as partial redundancy elimination and instruction scheduling, are very effective in improving application performance but tend to create longer and potentially more complex live ranges. Typically the task of dealing with the increased register pressure is left to the register allocator. To avoid introduction of spill code which can reduce or completely eliminate the benefit of earlier optimizations, researchers have developed techniques such as live range splitting and rematerializatio.This paper describes prematerialization (PM), a novel method for reducing register pressure for VLIW architectures with nop instructions. PM and rematerialization both select "never killed" live ranges and break them up by introducing one or more definitions close to the uses. However, while rematerialization is applied to live ranges selected for spilling during register allocation, PM relies on the availability of nop instructions and occurs prior to register allocation. PM simplifies register allocation by creating live ranges that are easier to color and less likely to spill. We have implemented prematerialization in HP-UX production compilers for the Intel® Itanium® architecture. Performance evaluation indicates that the proposed technique is effective in reducing register pressure inherent in highly optimized code.