Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
A tunable highly linear CMOS transconductor with 80dB of SFDR
Integration, the VLSI Journal
A highly linear CMOS transconductance amplifier in 180 nm process technology
Analog Integrated Circuits and Signal Processing
Linearity improvement of source degenerated transconductance amplifiers
Analog Integrated Circuits and Signal Processing
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This paper describes a method for analysis and design of MOS voltage-to-current converters (V-I converters or transconductors) and introduces a novel V-I converter circuit with significantly improved linearity performance. The proposed method uses harmonic compensation for the linearization of the V-I characteristics and introduces a normalized representation of the converter equations. The analysis is applied for several circuit topologies based on MOS differential pairs. The circuits are compared with respect to their current consumption, signal to noise ratio, achievable linearity and bandwidth. The minimum required current consumption for certain linearity and dynamic range is derived. The proposed novel V-I converter circuit uses a combination of local resistive feedback and cross-coupling. In this way, it achieves significant, simultaneous suppression of the third and the fifth order harmonic components in the transconductor output current. The implementation constraints and the performance of the new circuit solution are evaluated via simulations on transistor level. A standard digital 0.18 micrometer, 1.8V, CMOS process is used.