Theory of linear and integer programming
Theory of linear and integer programming
Integer and combinatorial optimization
Integer and combinatorial optimization
A practical algorithm for exact array dependence analysis
Communications of the ACM
Partitioning of processor arrays: a piecewise regular approach
Integration, the VLSI Journal - Special issue on algorithms and architectures
ICS '96 Proceedings of the 10th international conference on Supercomputing
Bounded scheduling of process networks
Bounded scheduling of process networks
Automatic storage management for parallel programs
Parallel Computing - Special issues on languages and compilers for parallel computers
Compaan: deriving process networks from Matlab for embedded signal processing architectures
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
YAPI: application modeling for signal processing systems
Proceedings of the 37th Annual Design Automation Conference
Optimizing memory usage in the polyhedral model
ACM Transactions on Programming Languages and Systems (TOPLAS)
A Methodology to Design Programmable Embedded Systems - The Y-Chart Approach
Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS
Memory Reuse Analysis in the Polyhedral Model
Euro-Par '96 Proceedings of the Second International Euro-Par Conference on Parallel Processing - Volume I
A Compile Time Based Approach for Solving Out-of-Order Communication in Kahn Process Networks
ASAP '02 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Deriving process networks from weakly dynamic applications in system-level design
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
System Design Using Kahn Process Networks: The Compaan/Laura Approach
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Translating affine nested-loop programs to process networks
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
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New embedded signal-processing architectures are emerging that are composed of loosely coupled heterogeneous components like CPUs or DSPs, specialized IP cores, reconfigurable units, or memories. We believe that these architectures should be programmed using the process network model of computation. To ease the mapping of applications, we are developing the Compaan compiler that automatically derives a process network (PN) description from an application written in Matlab or C. In this paper, we investigate a particular problem in nested loop programs, which is about classifying the interprocess communication in the PN representation of the nested loop program. The global memory arrays present in the code have to be replaced by a distributed communication structure used for communicating data between the network processes. We show that four types of communication exist, each exhibiting different requirements when realizing them in hardware or software. We first present two compile time tests that are based on integer linear programming to decide the type of the communication. In the second part of this paper, we present alternative classification techniques that have polynomial complexity. However, in some cases, those techniques do not give a definitive answer and the ILP tests have to be applied. All present tests are combined in a hybrid classification scheme that correctly classifies the interprocess communication. In only 5% of the cases to classify, we have to rely on integer linear programming while, in the remaining 95%, the alternative techniques presented in this paper are able to correctly classify each case. The hybrid classification scheme has become an important part of our Compaan compiler.