A fast pipelined multi-mode DES architecture operating in IP representation

Authors:
Sylvain Guilley;Philippe Hoogvorst;Renaud Pacalet
Affiliations:
GET/Télécom Paris, CNRS LTCI (UMR 5141), Département communication et électronique, France and 46 rue Barrault, 75634 Paris Cedex 13, France;GET/Télécom Paris, CNRS LTCI (UMR 5141), Département communication et électronique, France and 46 rue Barrault, 75634 Paris Cedex 13, France;GET/Télécom Paris, CNRS LTCI (UMR 5141), Département communication et électronique, France and Institut Eurecom BP 193, 2229 route des Crêtes, F-06904 Sophia-Antipolis Ced ...
Venue:
Integration, the VLSI Journal
Year:
2007

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Abstract

The Data Encryption Standard (DES) is a cipher that is still used in a broad range of applications, from smartcards, where it is often implemented as a tamper-resistant embedded co-processor, to PCs, where it is implemented in software (for instance, to compute crypt(3) on UNIX platforms). To the authors' knowledge, implementations of DES published so far are based on the straightforward application of the NIST standard. This article describes an innovative architecture that features a speed increase for both hardware and software implementations, compared to the state of the art. For example, the proposed architecture, at constant size, is about twice as fast as the state of the art for 3DES-CBC. The first contribution of this article is an hardware architecture that minimizes the computation time overhead caused by key and message loading. The second contribution is an optimal chaining of computations, typically required when ''operation modes'' are used. The optimization is made possible by a novel computation paradigm, called ''IP representation''.