Low-power baseband processing for wireless multimedia systems using unequal error protection
WTS'10 Proceedings of the 9th conference on Wireless telecommunications symposium
High-throughput layered LDPC decoding architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Unequal Error Protection Based on DVFS for JSCD in Low-Power Portable Multimedia Systems
ACM Transactions on Embedded Computing Systems (TECS)
Flexible LDPC decoder architectures
VLSI Design - Special issue on Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation
High speed architectures for finding the first two maximum/minimum values
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The VLSI implementation complexity of a low density parity check (LDPC) decoder is largely influenced by interconnect and the storage requirements. Here, the proposed layout-aware layered decoder architecture utilizes the data-reuse properties of min-sum, layered decoding and structured properties of array LDPC codes. This results in a significant reduction of logic and interconnects requirements of the decoder when compared to the state-of-the-art LDPC decoders. The ASIC implementation of the proposed fully parallel architecture achieves throughput of 4.6 Gbps (for a maximum of 15 iterations). The chip size is 2.3 mm x 2.3 mm in 0.13 micron technology.