High-speed & Low Area Hardware Architectures of the Whirlpool Hash Function

Authors:
Máire McLoone;Ciaran McIvor
Affiliations:
Institute of Electronics, Communications and Information Technology (ECIT), Queen's University Belfast, Belfast, UK BT3 9DT;Institute of Electronics, Communications and Information Technology (ECIT), Queen's University Belfast, Belfast, UK BT3 9DT
Venue:
Journal of VLSI Signal Processing Systems
Year:
2007

Citing 11
Cited 1

An Introduction to Cryptography

An Introduction to Cryptography
Handbook of Applied Cryptography

Handbook of Applied Cryptography
The Design of Rijndael

The Design of Rijndael
Comparative Analysis of the Hardware Implementations of Hash Functions SHA-1 and SHA-512

ISC '02 Proceedings of the 5th International Conference on Information Security
Compact and Efficient Encryption/Decryption Module for FPGA Implementation of the AES Rijndael Very Well Suited for Small Embedded Applications

ITCC '04 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 2 - Volume 2
Hardware Implementation Analysis of the MD5 Hash Algorithm

HICSS '05 Proceedings of the Proceedings of the 38th Annual Hawaii International Conference on System Sciences - Volume 09
ASIC-Hardware-Focused Comparison for Hash Functions MD5, RIPEMD-160, and SHS

ITCC '05 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'05) - Volume I - Volume 01
A compact FPGA implementation of the hash function whirlpool

Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
How to maximize software performance of symmetric primitives on pentium III and 4 processors

FSE'05 Proceedings of the 12th international conference on Fast Software Encryption
How to break MD5 and other hash functions

EUROCRYPT'05 Proceedings of the 24th annual international conference on Theory and Applications of Cryptographic Techniques
Efficient architecture and hardware implementation of the Whirlpool hash function

IEEE Transactions on Consumer Electronics

Compact ASIC Architectures for the 512-Bit Hash Function Whirlpool

Information Security Applications

Quantified Score

Hi-index	0.00

Visualization

Abstract

High-speed and low area hardware architectures of the Whirlpool hash function are presented in this paper. A full Look-up Table (LUT) based design is shown to be the fastest method by which to implement the non-linear layer of the algorithm in terms of logic. An unrolled Whirlpool architecture implemented on the Virtex XC4VLX100 device achieves a throughput of 4.9 Gbps. This is faster than a SHA-512 design implemented on the same device and other previously reported hash function architectures. A low area iterative architecture, which utilises 64-bit operations as opposed to full 512-bit operations, is also described. It runs at 430 Mbps and occupies 709 slices on a Virtex X4VLX15. This proves to be one of the smallest 512-bit hash function architectures currently available.