The Reduced Address Space (RAS) for Application Memory Authentication
ISC '08 Proceedings of the 11th international conference on Information Security
Making secure processors OS- and performance-friendly
ACM Transactions on Architecture and Code Optimization (TACO)
Hardware Mechanisms for Memory Authentication: A Survey of Existing Techniques and Engines
Transactions on Computational Science IV
Security extensions for integrity and confidentiality in embedded processors
Microprocessors & Microsystems
SHIELDSTRAP: making secure processors truly secure
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
IVEC: off-chip memory integrity protection for both security and reliability
Proceedings of the 37th annual international symposium on Computer architecture
An analysis of secure processor architectures
Transactions on computational science VII
Transactions on computational science X
Green secure processors: towards power-efficient secure processor design
Transactions on computational science X
SecureME: a hardware-software approach to full system security
Proceedings of the international conference on Supercomputing
i-NVMM: a secure non-volatile main memory system with incremental encryption
Proceedings of the 38th annual international symposium on Computer architecture
Authenticated Dictionaries: Real-World Costs and Trade-Offs
ACM Transactions on Information and System Security (TISSEC)
Bus and memory protection through chain-generated and tree-verified IV for multiprocessors systems
Future Generation Computer Systems
Proceedings of the ACM International Conference on Computing Frontiers
TSV: A novel energy efficient Memory Integrity Verification scheme for embedded systems
Journal of Systems Architecture: the EUROMICRO Journal
PHANTOM: practical oblivious computation in a secure processor
Proceedings of the 2013 ACM SIGSAC conference on Computer & communications security
An efficient run-time encryption scheme for non-volatile main memory
Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems
Memory encryption: A survey of existing techniques
ACM Computing Surveys (CSUR)
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In today's digital world, computer security issues have become increasingly important. In particular, researchers have proposed designs for secure processors which utilize hardware-based mem- ory encryption and integrity verification to protect the privacy and integrity of computation even from sophisticated physical attacks. However, currently proposed schemes remain hampered by prob- lems that make them impractical for use in today's computer sys- tems: lack of virtual memory and Inter-Process Communication support as well as excessive storage and performance overheads. In this paper, we propose 1) Address Independent Seed Encryption (AISE), a counter-mode based memory encryption scheme using a novel seed composition, and 2) Bonsai Merkle Trees (BMT), a novel Merkle Tree-based memory integrity verification technique, to elim- inate these system and performance issues associated with prior counter-mode memory encryption and Merkle Tree integrity veri- fication schemes. We present both a qualitative discussion and a quantitative analysis to illustrate the advantages of our techniques over previously proposed approaches in terms of complexity, feasi- bility, performance, and storage. Our results show that AISE+BMT reduces the overhead of prior memory encryption and integrity ver- ification schemes from 12% to 2% on average, while eliminating critical system-level problems.