Software pipelining: an effective scheduling technique for VLIW machines
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
Register allocation via hierarchical graph coloring
PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation
Register allocation for software pipelined loops
PLDI '92 Proceedings of the ACM SIGPLAN 1992 conference on Programming language design and implementation
Effective compiler support for predicated execution using the hyperblock
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Improvements to graph coloring register allocation
ACM Transactions on Programming Languages and Systems (TOPLAS)
Exact solution of large-scale, asymmetric traveling salesman problems
ACM Transactions on Mathematical Software (TOMS)
ACM Transactions on Programming Languages and Systems (TOPLAS)
Linear scan register allocation
ACM Transactions on Programming Languages and Systems (TOPLAS)
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Cluster assignment for high-performance embedded VLIW processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Register Allocation Framework Based on Hierarchical Cyclic Interval Graphs
CC '92 Proceedings of the 4th International Conference on Compiler Construction
Reducing register ports for higher speed and lower energy
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Region-based hierarchical operation partitioning for multicluster processors
PLDI '03 Proceedings of the ACM SIGPLAN 2003 conference on Programming language design and implementation
MICRO 14 Proceedings of the 14th annual workshop on Microprogramming
Optimistic register coalescing
ACM Transactions on Programming Languages and Systems (TOPLAS)
Removing communications in clustered microarchitectures through instruction replication
ACM Transactions on Architecture and Code Optimization (TACO)
Eulerian disjoint paths problem in grid graphs is NP-complete
Discrete Applied Mathematics
A global progressive register allocator
Proceedings of the 2006 ACM SIGPLAN conference on Programming language design and implementation
Modulo graph embedding: mapping applications onto coarse-grained reconfigurable architectures
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Inter-cluster communication in VLIW architectures
ACM Transactions on Architecture and Code Optimization (TACO)
Rotating Register Allocation for Enhanced Pipeline Scheduling
PACT '07 Proceedings of the 16th International Conference on Parallel Architecture and Compilation Techniques
Architecture enhancements for the ADRES coarse-grained reconfigurable array
HiPEAC'08 Proceedings of the 3rd international conference on High performance embedded architectures and compilers
An Efficient Memory Organization for High-ILP Inner Modem Baseband SDR Processors
Journal of Signal Processing Systems
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
REGIMap: register-aware application mapping on coarse-grained reconfigurable architectures (CGRAs)
Proceedings of the 50th Annual Design Automation Conference
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DSP architectures often feature multiple register files with sparse connections to a large set of ALUs. For such DSPs, traditional register allocation algorithms suffer from a lot of problems, including a lack of retargetability and phase-ordering problems. This paper studies alternative register allocation techniques based on placement and routing. Different register file models are studied and evaluated on a state-of-the art coarse-grained reconfigurable array DSP, together with a new post-pass register allocator for rotating register files.