How to Make a Correct Multiprocess Program Execute Correctly on a Multiprocessor
IEEE Transactions on Computers
Parallel Computer Architecture: A Hardware/Software Approach
Parallel Computer Architecture: A Hardware/Software Approach
Verifying a Multiprocessor Cache Controller Using Random Test Generation
IEEE Design & Test
Checking Cache-Coherence Protocols with TLA+
Formal Methods in System Design
Formal Design of Cache Memory Protocols in IBM
Formal Methods in System Design
Protocol Verification as a Hardware Design Aid
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Automatic Deductive Verification with Invisible Invariants
TACAS 2001 Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
Automaton: An Autonomous Coverage-Based Multiprocessor System Verification Environment
RSP '97 Proceedings of the 8th International Workshop on Rapid System Prototyping (RSP '97) Shortening the Path from Specification to Prototype
So Many States, So Little Time: Verifying Memory Coherence in the Cray X1
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
Generating concurrent test-programs with collisions for multi-processor verification
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
Introduction to the cell multiprocessor
IBM Journal of Research and Development - POWER5 and packaging
Reducing Verification Complexity of a Multicore Coherence Protocol Using Assume/Guarantee
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
Automated generation of directed tests for transition coverage in cache coherence protocols
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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The challenge of verification of multi-core and multi-processor designs grows dramatically with each new generation of systems produced today. Validation of memory coherence of such systems, which include multiple levels of cache and complex protocols, constitutes a major fraction of this task. Unfortunately, current tools are incapable of addressing these challenges, allowing bugs, which cause unpredictable software behavior and wrong computation results, to slip into hardware. In this work we present a scalable approach to the verification of memory coherence protocols in large multi-core and multi-processor systems. We accomplish this task through a distributed network of cooperating agents, which feed the processors with stimuli, each agent attempting to accomplish its own verification goals and support other agents on theirs as well. The agents can dynamically change the stimuli based on coverage and pressure observed during simulation. Since each agent has a minimal knowledge of the entire system, their communication and decision process is greatly simplified. Moreover, since the agents' view of the system is linear in the number of nodes in it, our approach can be efficiently scaled to target large multi-core systems. Experimental results on two common coherence protocols and a range of multi-core configurations demonstrate that our technique can reach high levels of coverage of the system-level protocol much faster than a constrained-random generator.