Wavelet based fault detection in analog VLSI circuits using neural networks

Authors:
P. Kalpana;K. Gunavathi
Affiliations:
Department of Electronics and Communication Engineering, PSG College of Technology, India;Department of Electronics and Communication Engineering, PSG College of Technology, India
Venue:
Applied Soft Computing
Year:
2008

Citing 6
Cited 3

Fault Diagnosis of Analog Circuits Using Bayesian Neural Networks with Wavelet Transform as Preprocessor

Journal of Electronic Testing: Theory and Applications
Mixed-Signal Circuit Classification in a Pseudo-Random Testing Scheme

Journal of Electronic Testing: Theory and Applications
Classification of Defective Analog Integrated Circuits Using Artificial Neural Networks

Journal of Electronic Testing: Theory and Applications
An Approach to the Classification of Mixed-Signal Circuits in a Pseudorandom Testing Scheme

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Pseudorandom testing for mixed-signal circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Detection of catastrophic faults in analog integrated circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Solving symmetric eigenvalue problem via genetic algorithms: Serial versus parallel implementation

Applied Soft Computing
A novel neural-network approach of analog fault diagnosis based on kernel discriminant analysis and particle swarm optimization

Applied Soft Computing
A New Optimal Test Node Selection Method for Analog Circuit

Journal of Electronic Testing: Theory and Applications

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper deals with a new method of testing analog VLSI circuits, using wavelet transform for analog circuit response analysis and artificial neural networks (ANN) for fault detection. Pseudo-random patterns generated by Linear Feedback Shift Register (LFSR) are used as input test patterns. The wavelet coefficients obtained for the fault-free and faulty cases of the circuits under test (CUT) are used to train the neural network. Two different architectures, back propagation and probabilistic neural networks are trained with the test data. To minimize the neural network architecture, normalization and principal component analysis are done on the input data before it is applied to the neural network. The proposed method is validated with two IEEE benchmark circuits, namely, the operational amplifier and state variable filter.