TAPE: thermal-aware agent-based power economy for multi/many-core architectures
Proceedings of the 2009 International Conference on Computer-Aided Design
Power, interface, and integration: handset chipset design issues
IEEE Communications Magazine
Agent-based thermal management using real-time I/O communication relocation for 3D many-cores
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Fine-grained hardware/software methodology for process migration in MPSoCs
Proceedings of the International Conference on Computer-Aided Design
RASTER: runtime adaptive spatial/temporal error resiliency for embedded processors
Proceedings of the 50th Annual Design Automation Conference
Dynamic cache management in multi-core architectures through run-time adaptation
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Reli: hardware/software checkpoint and recovery scheme for embedded processors
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
DHASER: dynamic heterogeneous adaptation for soft-error resiliency in ASIP-based multi-core systems
Proceedings of the International Conference on Computer-Aided Design
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The ability to stay on pace with Moore's law has been critical in providing for exponentially increasing computation capabilities per unit cost, and thus regularly enabling new applications. Maintaining this pace has always been challenging, but the challenges loom even larger as we approach the physical and economic limits of technology scaling. The resulting stress already is causing many companies to move toward fabless and fablight business models, with increased emphasis on system-level design technology. Another observable trend is the decline of ASICs and the corresponding growth in programmable platforms. These changes challenge traditional design technologies such as test and verification, and their interaction with emerging issues related to variability, reliability, and migration to post-silicon devices. This article proposes a roadmap of potential solutions for the future, based on managing massive concurrency, increasing self-adaptivity and resiliency, and adopting new computation models.