Design and validation of computer protocols
Design and validation of computer protocols
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A Translator of Java Programs to TADDs
Fundamenta Informaticae - Concurrency Specification and Programming (CS&P)
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VerICS is a tool for the automated verification of timed automata and protocols written in both the Intermediate Language and the specification language Estelle. Recently, the tool has been extended to work with Timed Automata with Discrete Data and with multi-agent systems. This paper presents a prototype Timed Automata with Discrete Data model of Java programs. In addition, we show how to use the model together with the verification core of VerICS to validate the well-known alternating bit protocol written in Java.