Robust synchronization of absolute and difference clocks over networks

Authors:
Darryl Veitch;Julien Ridoux;Satish Babu Korada
Affiliations:
ARC Special Centre for Ultra-Broadband Information Networks, National ICT Australia, Department of Electrical and Electronic Engineering, University of Melbourne, Victoria, Australia;ARC Special Centre for Ultra-Broadband Information Networks, National ICT Australia, Department of Electrical and Electronic Engineering, University of Melbourne, Victoria, Australia;École Polytechnique Fédérale de Lausanne, Lausanne, Switzerland
Venue:
IEEE/ACM Transactions on Networking (TON)
Year:
2009

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Abstract

We present a detailed re-examination of the problem of inexpensive yet accurate clock synchronization for networked devices. Based on an empirically validated, parsimonious abstraction of the CPU oscillator as a timing source, accessible via the TSC register in popular PC architectures, we build on the key observation that the measurement of time differences, and absolute time, requires separate clocks, both at a conceptual level and practically, with distinct algorithmic, robustness, and accuracy characteristics. Combined with round-trip time based filtering of network delays between the host and the remote time server, we define robust algorithms for the synchronization of the absolute and difference TSCclocks over a network. We demonstrate the effectiveness of the principles, and algorithms using months of real data collected using multiple servers. We give detailed performance results for a full implementation running live and unsupervised under numerous scenarios, which show very high reliability, and accuracy approaching fundamental limits due to host system noise. Our synchronization algorithms are inherently robust to many factors including packet loss, server outages, route changes, and network congestion.