Compositional, Dynamic Cache Management for Embedded Chip Multiprocessors

  • Authors:

  • Anca M. Molnos;Sorin D. Cotofana;Marc J. Heijligers;Jos T. Eijndhoven

  • Affiliations:

  • NXP Semiconductors, Eindhoven, The Netherlands and Technical University of Delft, Delft, The Netherlands;Technical University of Delft, Delft, The Netherlands;NXP Semiconductors, Eindhoven, The Netherlands;Vector Fabrics, Eindhoven, The Netherlands

  • Venue:
  • Journal of Signal Processing Systems
  • Year:
  • 2009

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Abstract

This paper proposes a dynamic cache repartitioning technique that enhances compositionality on platforms executing media applications with multiple utilization scenarios. Because the repartitioning between scenarios requires a cache flush, two undesired effects may occur: (1) in particular, the execution of critical tasks may be disturbed and (2) in general, a performance penalty is involved. To cope with these effects we propose a method which: (1) determines, at design time, the cache footprint of each tasks, such that it creates the premises for critical tasks safety, and minimum flush in general, and (2) enforces, at run-time, the design time determined cache footprints and further decreases the flush penalty. We implement our dynamic cache management strategy on a CAKE multiprocessor with 4 Trimedia cores. The experimental workload consists of 6 multimedia applications, each of which formed by multiple tasks belonging to an extended MediaBench suite. We found on average that: (1) the relative variations of critical tasks execution time are less than 0.1%, regardless of the scenario switching frequency, (2) for realistic scenario switching frequencies the inter-task cache interference is at most 4% for the repartitioned cache, whereas for the shared cache it reaches 68%, and (3) the off-chip memory traffic reduces with 60%, and the performance (in cycles per instruction) enhances with 10%, when compared with the shared cache.