Patterns in property specifications for finite-state verification
Proceedings of the 21st international conference on Software engineering
Implementing Statecharts in PROMELA/SPIN
WIFT '98 Proceedings of the Second IEEE Workshop on Industrial Strength Formal Specification Techniques
Unified Modeling Language Reference Manual, The (2nd Edition)
Unified Modeling Language Reference Manual, The (2nd Edition)
A Formal Semantics of Timed Activity Diagrams and its PROMELA Translation
APSEC '05 Proceedings of the 12th Asia-Pacific Software Engineering Conference
A Unified Approach for Verification and Validation of Systems and Software Engineering Models
ECBS '06 Proceedings of the 13th Annual IEEE International Symposium and Workshop on Engineering of Computer Based Systems
A scenario based notation for specifying temporal properties
Proceedings of the 2006 international workshop on Scenarios and state machines: models, algorithms, and tools
Towards Model-based Verification of BPEL with Model Checking
CIT '06 Proceedings of the Sixth IEEE International Conference on Computer and Information Technology
Four Automated Approaches to Analyze the Quality of UML Sequence Diagrams
COMPSAC '07 Proceedings of the 31st Annual International Computer Software and Applications Conference - Volume 02
Property Specification and Static Verification of UML Models
ARES '08 Proceedings of the 2008 Third International Conference on Availability, Reliability and Security
Model checking of UML 2.0 interactions
MoDELS'06 Proceedings of the 2006 international conference on Models in software engineering
Towards semantics-aware merge support in optimistic model versioning
MODELS'11 Proceedings of the 2011th international conference on Models in Software Engineering
Towards a generic verification methodology for system models
Proceedings of the Conference on Design, Automation and Test in Europe
A formal verification framework for SysML activity diagrams
Expert Systems with Applications: An International Journal
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A major challenge in software development process is to advance error detection to early phases of the software life cycle. For this purpose, the Verification and Validation (V&V) of UML diagrams play a very important role in detecting flaws at the design phase. It has a distinct importance for software security, where it is crucial to detect security flaws before they can be exploited. This paper presents a formal V&V technique for one of the most popular UML diagrams: sequence diagrams. The proposed approach creates a PROMELA-based model from UML interactions expressed in sequence diagrams, and uses SPIN model checker to simulate the execution and to verify properties written in Linear Temporal Logic (LTL). The whole technique is implemented as an Eclipse plugin, which hides the model-checking formalism from the user. The main contribution of this work is to provide an efficient mechanism to be able to track the execution state of an interaction, which allows designers to write relevant properties involving send/receive events and source/destination of messages using LTL. Another important contribution is the definition of the PROMELA structure that provides a precise semantics of most of the newly UML 2.0 introduced combined fragments, allowing the execution of complex interactions. Finally, we illustrate the benefits of our approach through a security-related case study in a real world scenario.