Advanced animation and rendering techniques
Advanced animation and rendering techniques
The design and analysis of a cache architecture for texture mapping
Proceedings of the 24th annual international symposium on Computer architecture
Optimization of mesh locality for transparent vertex caching
Proceedings of the 26th annual conference on Computer graphics and interactive techniques
Towards hardware implementation of loop subdivision
HWWS '00 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Adaptive view dependent tessellation of displacement maps
HWWS '00 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Watertight tessellation using forward differencing
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Hardware support for adaptive subdivision surface rendering
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Rapid evaluation of Catmull-Clark subdivision surfaces
Proceedings of the seventh international conference on 3D Web technology
Generic mesh refinement on GPU
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware
A realtime GPU subdivision kernel
ACM SIGGRAPH 2005 Papers
GPU-based trimming and tessellation of NURBS and T-Spline surfaces
ACM SIGGRAPH 2005 Papers
IEEE Micro
ACM SIGGRAPH 2006 Papers
Efficient depth buffer compression
GH '06 Proceedings of the 21st ACM SIGGRAPH/EUROGRAPHICS symposium on Graphics hardware
Approximating Catmull-Clark subdivision surfaces with bicubic patches
ACM Transactions on Graphics (TOG)
The State of the Art in Mobile Graphics Research
IEEE Computer Graphics and Applications
A mobile 3-D display processor with a bandwidth-saving subdivider
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Technical Section: Energy-aware hybrid precision selection framework for mobile GPUs
Computers and Graphics
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In this paper, we propose an architecture of tessellation hardware to save memory bandwidth in a mobile multimedia processor. To reduce the implementation overhead, floating-point computations of tessellation are accelerated by the conventional GPU pipeline, and only tessellation-specific control logic is handled by an additional hardware unit. Tightly coupled with a vertex shader, the additional unit dynamically produces topological configurations and parametric coordinates of refinement patterns in the type of indexed triangle strips for object-level adaptive tessellation. The topological configurations improve the efficiency of the vertex cache so as to avoid redundant shader operations. Since the proposed tessellator is area-efficient and does not require intermediate memory accesses, its architecture is especially appropriate for the mobile environment, which adopts a shared bus and unified external memory architecture. The proposed tessellator is fabricated on a chip using 0.18@mm CMOS technology. With 6.2% additional hardware for a dual-core vertex shader, the implemented chip performs 120Mvertices/s vertex shading and saves memory bandwidth up to 250 times in tessellation.