A multilevel algorithm for partitioning graphs
Supercomputing '95 Proceedings of the 1995 ACM/IEEE conference on Supercomputing
Graph partitioning models for parallel computing
Parallel Computing - Special issue on graph partioning and parallel computing
Algorithms for VLSI Physical Design Automation
Algorithms for VLSI Physical Design Automation
Partitioning sequential programs for CAD using a three-step approach
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Mesh Partitioning: A Multilevel Balancing and Refinement Algorithm
SIAM Journal on Scientific Computing
A Mixed Heuristic for Circuit Partitioning
Computational Optimization and Applications
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
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Code partitioning is the problem of dividing sections of code among a set of processors for execution in parallel taking into account the communication overhead between the processors. Code partitioning of large amounts of code onto numerous processors requires variations to the classical partitioning algorithms, in part due to the memory and time requirements to partition a large set of data, but also due to the nature of the target machine and multiple constraints imposed by its architectural features. In this paper, we present our experience in the design of enhancements to the classical multi-level k-way partitioning algorithm to deal with large graphs of over 1 million nodes, 5 constraints, and nodes of irregular size. Our algorithm was implemented to produce code for a massively parallel machine of up to 40,000 processors, and forms part of a hardware description language compiler. The algorithm and the compiler were tested on RTL designs for a next generation SPARC® processor. We present performance results and comparisons for partitioning multi-processor hardware designs.