A Mixed Heuristic for Circuit Partitioning

  • Authors:

  • C. Gil;J. Ortega;M. G. Montoya;R. Baños

  • Affiliations:

  • Departamento de Arquitectura de Computadores y Electrónica, Universidad de Almería, La Cañada de San Urbano s/n, 04120 Almería, SPAIN. cgil@ace.ual.es;Departamento de Arquitectura y Tecnología de Computadores, Universidad de Granada, Campus de Fuentenueva, Granada, SPAIN. julio@atc.ugr.es;Departamento de Arquitectura de Computadores y Electrónica, Universidad de Almería, La Cañada de San Urbano s/n, 04120 Almería, SPAIN. mari@ace.ual.es;Departamento de Arquitectura de Computadores y Electrónica, Universidad de Almería, La Cañada de San Urbano s/n, 04120 Almería, SPAIN

  • Venue:
  • Computational Optimization and Applications
  • Year:
  • 2002

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Abstract

As general-purpose parallel computers are increasingly being used to speed up different VLSI applications, the development of parallel algorithms for circuit testing, logic minimization and simulation, HDL-based synthesis, etc. is currently a field of increasing research activity. This paper describes a circuit partitioning algorithm which mixes Simulated Annealing (SA) and Tabu Search (TS) heuristics. The goal of such an algorithm is to obtain a balanced distribution of the target circuit among the processors of the multicomputer allowing a parallel CAD application for Test Pattern Generation to provide good efficiency. The results obtained indicate that the proposed algorithm outperforms both a pure Simulated Annealing and a Tabu Search. Moreover, the usefulness of the algorithm in providing a balanced workload distribution is demonstrated by the efficiency results obtained by a topological partitioning parallel test-pattern generator in which the proposed algorithm has been included. An extented algorithm that works with general graphs to compare our approach with other state of the art algorithms has been also included.