VLSI architecture for MRF based stereo matching

Authors:
Sungchan Park;Chao Chen;Hong Jeong
Affiliations:
Pohang University of Science and Technology, Electronic amd Electrical Engineering, Pohang, Kyungbuk, South Korea;Pohang University of Science and Technology, Electronic amd Electrical Engineering, Pohang, Kyungbuk, South Korea;Pohang University of Science and Technology, Electronic amd Electrical Engineering, Pohang, Kyungbuk, South Korea
Venue:
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
Year:
2007

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Abstract

As a step towards real-time stereo on 2D markov random field (MRF), we will present fast belief propagation (FBP) VLSI architecture for stereo matching, which has a parallel, distributed and memory-efficient structure and lowest error rates among the real-time systems. FBP can reduce memory complexities by 17 times smaller than belief propagation (BP) and output 320x240 disparity image of 32 levels with 320 parallel processors on 2 Xilinx FPGAs at 30 frames/s. Multiple chips can be cascaded to increase computation speed due to its linear array architecture. Our structure is more adequate for high resolution and real-time applications like 3D video conference, multi-view coding and 3D modelling.