Multiprocessor mapping of process networks: a JPEG decoding case study
Proceedings of the 15th international symposium on System Synthesis
Algorithmic transformation techniques for efficient exploration of alternative application instances
Proceedings of the tenth international symposium on Hardware/software codesign
Automatic synthesis of system on chip multiprocessor architectures for process networks
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
pn: a tool for improved derivation of process networks
EURASIP Journal on Embedded Systems
Parametric throughput analysis of synchronous data flow graphs
Proceedings of the conference on Design, automation and test in Europe
A generalized static data flow clustering algorithm for mpsoc scheduling of multimedia applications
EMSOFT '08 Proceedings of the 8th ACM international conference on Embedded software
Practical and Accurate Throughput Analysis with the Cyclo Static Dataflow Model
MASCOTS '07 Proceedings of the 2007 15th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems
Automatic buffer sizing for rate-constrained KPN applications on multiprocessor system-on-chip
HLDVT '07 Proceedings of the 2007 IEEE International High Level Design Validation and Test Workshop
On compile-time evaluation of process partitioning transformations for Kahn process networks
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Systematic and Automated Multiprocessor System Design, Programming, and Implementation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modeling adaptive streaming applications with parameterized polyhedral process networks
Proceedings of the 48th Design Automation Conference
Communication-aware mapping of KPN applications onto heterogeneous MPSoCs
Proceedings of the 49th Annual Design Automation Conference
A rule-based quasi-static scheduling approach for static islands in dynamic dataflow graphs
ACM Transactions on Embedded Computing Systems (TECS)
Design space pruning through hybrid analysis in system-level design space exploration
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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We use the polyhedral process network (PPN) model of computation to program embedded Multi-Processor Systems on Chip (MPSoCs) platforms. If a designer wants to reduce the number of processes in a network due to resource constraints, for example, then the process merging transformation can be used to achieve this. We present a compile-time approach to evaluate the system throughput of PPNs in order to select a merging candidate which gives a system throughput as close as possible to the original PPN. We show results for two experiments on the ESPAM platform prototyped on a Xilinx Virtex 2 Pro FPGA.