Static scheduling of synchronous data flow programs for digital signal processing
IEEE Transactions on Computers
Multiprocessor mapping of process networks: a JPEG decoding case study
Proceedings of the 15th international symposium on System Synthesis
Automatic Parallelization in the Polytope Model
The Data Parallel Programming Model: Foundations, HPF Realization, and Scientific Applications
Scheduling dynamic dataflow graphs with bounded memory using the token flow model
Scheduling dynamic dataflow graphs with bounded memory using the token flow model
System Design Using Kahn Process Networks: The Compaan/Laura Approach
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Proceedings of the 4th ACM international conference on Embedded software
Code Generation in the Polyhedral Model Is Easier Than You Think
Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques
Scalable and structured scheduling
International Journal of Parallel Programming
pn: a tool for improved derivation of process networks
EURASIP Journal on Embedded Systems
Electronic system-level synthesis methodologies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Throughput modeling to evaluate process merging transformations in polyhedral process networks
Proceedings of the Conference on Design, Automation and Test in Europe
Lucy-n: a n-synchronous extension of Lustre
MPC'10 Proceedings of the 10th international conference on Mathematics of program construction
IEEE Transactions on Signal Processing
Parameterized dataflow modeling for DSP systems
IEEE Transactions on Signal Processing
Systematic and Automated Multiprocessor System Design, Programming, and Implementation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Worst-case throughput analysis of real-time dynamic streaming applications
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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The Kahn Process Network (KPN) model is a widely used model-of-computation to specify and map streaming applications onto multiprocessor systems-on-chips. In general, KPNs are difficult to analyze at design-time. Thus a special case of the KPN model, called Polyhedral Process Networks (PPN), has been proposed to address the analyzability issue. However, the PPN model is not able to capture adaptive/dynamic behavior. Such behavior is usually expressed by using parameters which values are reconfigured at run-time. To model the adaptive/dynamic applications, in this paper we introduce an extension of the PPN model, called Parameterized Polyhedral Process Networks (P3N), which still provides design-time analyzability to some extent. We first formally define the P3N model and its operational semantics. In addition, we devise a design-time analysis to extract relations between parameters. Based on the analysis, we propose an approach to ensure that consistent execution of the P3N model is preserved at run-time. Using an FPGA-based MPSoC platform, we present a performance evaluation of the possible overhead caused by the run-time reconfiguration.