A VLSI pyramid chip for multiresolution image analysis
International Journal of Computer Vision - Special issue: VLSI for computer vision
Digital Image Warping
Measurement of Image Velocity
Calculating Dense Disparity Maps from Color Stereo Images, an Efficient Implementation
International Journal of Computer Vision
Real-Time Correlation-Based Stereo Vision with Reduced Border Errors
International Journal of Computer Vision
Non-parametric Local Transforms for Computing Visual Correspondence
ECCV '94 Proceedings of the Third European Conference-Volume II on Computer Vision - Volume II
A Stereo Machine for Video-Rate Dense Depth Mapping and Its New Applications
CVPR '96 Proceedings of the 1996 Conference on Computer Vision and Pattern Recognition (CVPR '96)
Real-time stereo vision on the PARTS reconfigurable computer
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
A Simple Stereo Algorithm to Recover Precise Object Boundaries and Smooth Surfaces
SMBV '01 Proceedings of the IEEE Workshop on Stereo and Multi-Baseline Vision (SMBV'01)
Video-rate stereo depth measurement on programmable hardware
CVPR'03 Proceedings of the 2003 IEEE computer society conference on Computer vision and pattern recognition
Multi-resolution real-time stereo on commodity graphics hardware
CVPR'03 Proceedings of the 2003 IEEE computer society conference on Computer vision and pattern recognition
A Real-Time Low-Power Stereo Vision Engine Using Semi-Global Matching
ICVS '09 Proceedings of the 7th International Conference on Computer Vision Systems: Computer Vision Systems
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In this paper, we discuss the design and implementation of a Field-Programmable Gate Array (FPGA) based stereo depth measurement system that is capable of handling a very large disparity range. The system performs rectification of the input video stream and a left-right consistency check to improve the accuracy of the results and generates subpixel disparities at 30 frames/second on 480 × 640 images. The system is based on the Local Weighted Phase-Correlation algorithm [9] which estimates disparity using a multi-scale and multi-orientation approach. Though FPGAs are ideal devices to exploit the inherent parallelism in many computer vision algorithms, they have a finite resource capacity which poses a challenge when adapting a system to deal with large image sizes or disparity ranges. In this work, we take advantage of the temporal information available in a video sequence to design a novel architecture for the correlation unit to achieve correlation over a large range while keeping the resource utilisation very low as compared to a naive approach of designing a correlation unit in hardware.