Cache coherence protocols: evaluation using a multiprocessor simulation model
ACM Transactions on Computer Systems (TOCS)
ACM Transactions on Computer Systems (TOCS)
Synthetic Traces for Trace-Driven Simulation of Cache Memories
IEEE Transactions on Computers
On the accuracy of memory reference models
Proceedings of the 7th international conference on Computer performance evaluation : modelling techniques and tools: modelling techniques and tools
Principles of Optimal Page Replacement
Journal of the ACM (JACM)
ACM Computing Surveys (CSUR)
System performance evaluation: survey and appraisal
Communications of the ACM
Using locality surfaces to characterize the SPECint 2000 benchmark suite
Workload characterization of emerging computer applications
Compile-Time Based Performance Prediction
LCPC '99 Proceedings of the 12th International Workshop on Languages and Compilers for Parallel Computing
Issues in Trace-Driven Simulation
Performance Evaluation of Computer and Communication Systems, Joint Tutorial Papers of Performance '93 and Sigmetrics '93
A framework for performance modeling and prediction
Proceedings of the 2002 ACM/IEEE conference on Supercomputing
The Inaccuracy of Trace-Driven Simulation Using Incomplete Multiprogramming Trace Data
MASCOTS '96 Proceedings of the 4th International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems
Computer Architecture: A Quantitative Approach
Computer Architecture: A Quantitative Approach
Compressed Pattern Matching for Sequitur
DCC '01 Proceedings of the Data Compression Conference
Low cost trace-driven memory simulation using SimPoint
ACM SIGARCH Computer Architecture News - Special issue on the 2005 workshop on binary instrumentation and application
StatCache: a probabilistic approach to efficient and accurate data locality analysis
ISPASS '04 Proceedings of the 2004 IEEE International Symposium on Performance Analysis of Systems and Software
Reducing time and space costs of memory tracing
Reducing time and space costs of memory tracing
Synthetic Trace-Driven Simulation of Cache Memory
AINAW '07 Proceedings of the 21st International Conference on Advanced Information Networking and Applications Workshops - Volume 01
IEEE Transactions on Computers
AFIPS '72 (Spring) Proceedings of the May 16-18, 1972, spring joint computer conference
Evaluation techniques for storage hierarchies
IBM Systems Journal
An idiom-finding tool for increasing productivity of accelerators
Proceedings of the international conference on Supercomputing
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Memory address traces are an important information source; they drive memory simulations for performance modeling, systems design and application tuning. For long running applications, the direct use of an address trace is complicated by its size. Previous attempts to reduce trace size incurred a substantial penalty with respect to trace accuracy. We propose a novel method of memory profiling that enables the generation of highly accurate synthetic traces with space requirements typically under 1% of the original traces. We demonstrate the synthetic trace accuracy in terms of cache hit rates, spatial-temporal locality scores and locality surfaces. Simulated cache hit rates from synthetic traces are within 3.5% of observed and on average are within 1.0% for L1 cache. Our profiles are on average 60 times smaller than compressed traces. The combination of small profile sizes and high similarity to original traces makes our technique uniquely applicable to performance modeling and trace driven simulation of large-scale parallel scientific applications.