Decoupled inter- and intra-application scheduling for composable and robust embedded MPSoC platforms

  • Authors:

  • Anca Molnos;Ashkan Beyranvand Nejad;Ba Thang Nguyen;Sorin Cotofana;Kees Goossens

  • Affiliations:

  • Technical University of Delft, The Netherlands;Technical University of Delft, The Netherlands;DEK Technologies, Vietnam;Technical University of Delft, The Netherlands;Technical University of Eindhoven, The Netherlands

  • Venue:
  • Proceedings of the 15th International Workshop on Software and Compilers for Embedded Systems
  • Year:
  • 2012

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Abstract

Systems-on-Chip (SoCs) typically implement complex applications, each consisting of multiple tasks. Several applications share the SoC cores, to reduce cost. Applications have mixed time-criticality, i.e., real-time or not, and are typically developed together with their schedulers, by different parties. Composability, i.e., complete functional and temporal isolation between applications, is an SoC property required to enable fast integration and verification of applications. To achieve composability, an Operating System (OS) allocates processor time in quanta of constant duration. The OS executes first the application scheduler, then the corresponding task scheduler, to determine which task runs next. As the OS should be a trusted code base, both inter- and intra-application schedulers should be thoroughly analysed and verified. This is required anyway for real-time intra-application schedulers. But for non-real-time applications, a costly effort is required to achieve the desired confidence level in their intra-application schedulers. In this paper we propose a light-weight, real-time OS implementation that overcomes these limitations. It separates the two arbitration levels, and requires only the inter-application scheduler to run in OS time. The intra-application scheduler runs in user time, and is therefore not trusted code. This approach allows each application to execute its own specialised task scheduler. We evaluated the practical implications of our proposal on an SoC modelled in FPGA, running an H264 and a JPEG decoder and we found that composability is preserved and performance is improved with up to 37%.