A Path Sensitization Technique for Testing of Switched Capacitor Circuits
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Built-In-Self-Testing Techniques for Programmable Capacitor Arrays
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Built-In-Self-Testing Techniques for Programmable Capacitor Arrays
Journal of Electronic Testing: Theory and Applications
Oscillation Test Scheme of SC Biquad Filters Based on Internal Reconfiguration
Journal of Electronic Testing: Theory and Applications
Complex oscillation-based test and its application to analog filters
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special issue on ISCAS 2009
| Hi-index | 0.03 |
Parametric faults are a significant cause of incorrect operation in analog circuits. Many design for test techniques for analog circuits are ineffective at detecting multiple parametric faults because either their accuracy is poor, or the circuit is not tested in the configuration in which it is used. We present a design for test (DFT) scheme that offers the accuracy needed to test high-quality circuits. The DFT scheme is based on a circuit that digitally measures the ratio of a pair of capacitors. The circuit is used to characterize the transfer function of a switched capacitor circuit, which is usually determined by capacitor ratios. In our DFT scheme, capacitor ratios can be measured to within 0.01% accuracy and filter parameters can be shown to be satisfied to within 0.1% accuracy. With this characterization process, a filter can be directly shown to satisfy all specifications that depend on capacitor ratios. We believe the accuracy of our approach is at least an order of magnitude greater than that offered by any other DFT scheme reported in the literature