A comprehensive integration infrastructure for embedded system design

  • Authors:
  • JesúS Barba;Fernando RincóN;Francisco Moya;Julio Daniel Dondo;Juan Carlos LóPez

  • Affiliations:
  • Department of Technology and Information Systems, School of Computer Science, University of Castilla-La Mancha, Spain;Department of Technology and Information Systems, School of Computer Science, University of Castilla-La Mancha, Spain;Department of Technology and Information Systems, School of Computer Science, University of Castilla-La Mancha, Spain;Department of Technology and Information Systems, School of Computer Science, University of Castilla-La Mancha, Spain;Department of Technology and Information Systems, School of Computer Science, University of Castilla-La Mancha, Spain

  • Venue:
  • Microprocessors & Microsystems
  • Year:
  • 2012

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Abstract

A System-on-a-Chip (SoC) is the most successful example of how the evolution of the chip integration technology allows the manufacture of complex embedded systems. However, the bulk of the design effort, to efficiently combine the HW and SW components in a SoC, still resides in the HW/SW interfacing architecture. A good HW/SW integration strategy has a positive impact either in performance, efficiency, development times, productivity or reutilization of platforms for future designs. In this paper, we present an object-oriented approach to cope with the HW/SW integration problem in SoCs. The Object-Oriented Communication Engine (OOCE) is a system-level middleware particularly designed for SoCs which provides a high-level and homogeneous view of the system components based on the Distributed Object paradigm. Communication between components is abstracted by means of a HW implementation of the Remote Method Invocation semantics and all the SW and HW adapters are automatically generated from functional descriptions of the components interface. The resulting communication infrastructure simplifies the integration effort required and makes the embedded software more resilient to changes in the HW platform. To prove the viability and efficiency of our proposal a prototype implementation on the Xilinx ML505 evaluation platform has been performed.