Architectural power analysis: the dual bit type method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analytical estimation of transition activity from word-level signal statistics
DAC '97 Proceedings of the 34th annual Design Automation Conference
Low-power realization of FIR filters on programmable DSP's
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DSP Processor Fundamentals: Architectures and Features
DSP Processor Fundamentals: Architectures and Features
Digital Signal Processing with Field Programmable Gate Arrays with Cdrom
Digital Signal Processing with Field Programmable Gate Arrays with Cdrom
Power efficient data path synthesis of sum-of-products computations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Transition-activity aware design of reduction-stages for parallel multipliers
Proceedings of the 17th ACM Great Lakes symposium on VLSI
IEEE Transactions on Signal Processing
Performance limit of finite wordlength FIR digital filters
IEEE Transactions on Signal Processing
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In this work we consider coefficient reordering for low power realization of FIR filters on fixed-point multiply-accumulate (MAC) based architectures, such as DSP processors. Compared to previous work we consider the input data correlation in the ordering optimization. For this we model the input data using the dual bit type approach. Results show that compared with just optimizing the number of switches between coefficients, the proposed method works better when the input data is correlated, which can be assumed for most applications.