Procedural elements for computer graphics
Procedural elements for computer graphics
Frame-buffer display architectures
Annual review of computer science vol. 1, 1986
A parallel processor architecture for graphics arithmetic operations
SIGGRAPH '87 Proceedings of the 14th annual conference on Computer graphics and interactive techniques
Hardware acceleration for Window systems
SIGGRAPH '89 Proceedings of the 16th annual conference on Computer graphics and interactive techniques
The pixel machine: a parallel image computer
SIGGRAPH '89 Proceedings of the 16th annual conference on Computer graphics and interactive techniques
A characterization of ten rasterization techniques
SIGGRAPH '89 Proceedings of the 16th annual conference on Computer graphics and interactive techniques
High-performance polygon rendering
SIGGRAPH '88 Proceedings of the 15th annual conference on Computer graphics and interactive techniques
A display system for the Stellar graphics supercomputer model GS1000
SIGGRAPH '88 Proceedings of the 15th annual conference on Computer graphics and interactive techniques
The Silicon Graphics 4D/240GTX Superworkstation
IEEE Computer Graphics and Applications
3DGRP - A High Performance Graphics System
Proceedings of the IFIP WG 5.10 International Working Conference on Workstations for Experiments
The Geometry Engine: A VLSI Geometry System for Graphics
SIGGRAPH '82 Proceedings of the 9th annual conference on Computer graphics and interactive techniques
Memory Design for Raster Graphics Displays
IEEE Computer Graphics and Applications
| Hi-index | 0.00 |
Today's workstation users demand high computational performance combined with powerful graphics and a comfortable window system. Existing and forthcoming standards like OKS-3D, PHIGS/PHIGS+, X Window System, and PEX have to be supported optimally. This paper presents the architecture of a graphics engine designed to meet the above requirements. Utilizing a distributed frame buffer pixel access with a high bandwidth is achieved. Several functions of a window management system like clipping at arbitrarily shaped window boundaries, fast copying of windows and performing Bit-Block-Transfer operations (BitBlT) are performed by hardware. Finally, a homogeneous and load-adaptive multiprocessor configuration for geometry and rendering calculation is described.