Microwave transistor amplifiers (2nd ed.): analysis and design
Microwave transistor amplifiers (2nd ed.): analysis and design
A low-power and high-gain fully integrated CMOS LNA
Microelectronics Journal
An Adaptive Body-Bias Generator for Low Voltage CMOS VLSI Circuits
International Journal of Distributed Sensor Networks - Advances on Heterogeneous Wireless Sensor Networks
Low power and high gain current reuse LNA with modified input matching and inter-stage inductors
Microelectronics Journal
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
A 0.9-V, 7-mW UWB LNA for 3.1-10.6-GHz wireless applications in 0.18-µm CMOS technology
Microelectronics Journal
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In this paper, a low power ultra-wideband (UWB) CMOS LNA was designed exploiting source inductive degeneration technique operating in the frequency range of 3.1-10.6GHz. In order to achieve low noise figure and high linearity simultaneously, a modified three-stage UWB LNA with inter-stage inductors was proposed. Forward Body-Biased (FBB) technique was used to reduce threshold voltage and power consumption at the first and third stages. The second stage is a push-pull topology exploiting the complementary characteristics of NMOS and PMOS transistors to enhance the linearity performance. The proposed LNA was simulated in standard 0.13@mm CMOS process. A gain of 19.5+/-1.5dB within the entire band was exhibited. The simulated noise figure (NF) was 1-3.9dB within the bandwidth. A maximum simulated third-order input intercept point (IIP3) of 4.56dBm while consuming 4.1mW from a 0.6 power supply was achieved. The simulated input return loss (S"1"1) was less than -5dB from 4.9 to 12.1GHz. The output return loss (S"2"2) was below -10.6dB and S"1"2 was better than -70.6dB.