STRAPS: A Software TRAnsPort System for low-level software
Journal of Systems and Software
COM: an 8080 simulator for the MC68000
Dr. Dobb's Journal
BYTE
Computer
Tutorial : reduced instruction set computers
Tutorial : reduced instruction set computers
Assemblers, Compilers, and Program Translation
Assemblers, Compilers, and Program Translation
Flow Analysis of Computer Programs
Flow Analysis of Computer Programs
Compiler Construction for Digital Computers
Compiler Construction for Digital Computers
Efficient implementation of the smalltalk-80 system
POPL '84 Proceedings of the 11th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Levels of representation of programs and the architecture of universal host machines
MICRO 11 Proceedings of the 11th annual workshop on Microprogramming
A software high performance APL interpreter
APL '79 Proceedings of the international conference on APL: part 1
The Dynamic Incremental Compiler of APL\3000
APL '79 Proceedings of the international conference on APL: part 1
An overview of the PL.8 compiler
SIGPLAN '82 Proceedings of the 1982 SIGPLAN symposium on Compiler construction
The Parallel Assignment Problem Redefined
IEEE Transactions on Software Engineering
A portable interface for on-the-fly instruction space modification
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Migrating a CISC computer family onto RISC via object code translation
ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems
Shade: a fast instruction-set simulator for execution profiling
SIGMETRICS '94 Proceedings of the 1994 ACM SIGMETRICS conference on Measurement and modeling of computer systems
Talisman: fast and accurate multicomputer simulation
Proceedings of the 1995 ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems
Performance impact of architectural features during binary to binary translation
PACT '95 Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques
A persistent rescheduled-page cache for low overhead object code compatibility in VLIW architectures
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Trace-driven memory simulation: a survey
ACM Computing Surveys (CSUR)
Direct execution models of processor behavior and performance
WSC '87 Proceedings of the 19th conference on Winter simulation
Optimizations and oracle parallelism with dynamic translation
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Binary translation and architecture convergence issues for IBM system/390
Proceedings of the 14th international conference on Supercomputing
The legal status of reverse engineering of computer software
Annals of Software Engineering
Motorola PowerPC Migration Tools-emulation and translation
COMPCON '96 Proceedings of the 41st IEEE International Computer Conference
A brief history of just-in-time
ACM Computing Surveys (CSUR)
Structuring the Kernel as a Toolkit of Extensible, Reusable Components
IWOOOS '95 Proceedings of the 4th International Workshop on Object-Orientation in Operating Systems
Software-based instruction caching for embedded processors
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
HDTrans: an open source, low-level dynamic instrumentation system
Proceedings of the 2nd international conference on Virtual execution environments
Ultra fast cycle-accurate compiled emulation of inorder pipelined architectures
Journal of Systems Architecture: the EUROMICRO Journal
A comparison of OS extension technologies
ATEC '96 Proceedings of the 1996 annual conference on USENIX Annual Technical Conference
High Speed CPU Simulation Using LTU Dynamic Binary Translation
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
A transformational approach to binary translation of delayed branches with applications to SPARC® and PA-RISC instructions sets
Generating low-overhead dynamic binary translators
Proceedings of the 3rd Annual Haifa Experimental Systems Conference
DisIRer: Converting a retargetable compiler into a multiplatform binary translator
ACM Transactions on Architecture and Code Optimization (TACO)
Generalized just-in-time trace compilation using a parallel task farm in a dynamic binary translator
Proceedings of the 32nd ACM SIGPLAN conference on Programming language design and implementation
Ultra fast cycle-accurate compiled emulation of inorder pipelined architectures
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Proceedings of the 13th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory for Embedded Systems
Optimizing indirect branches in a system-level dynamic binary translator
Proceedings of the 5th Annual International Systems and Storage Conference
ISC'07 Proceedings of the 10th international conference on Information Security
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Software simulation of one computer on another tends to be slow. Traditional simulators typically execute about 100 instructions on the host machine per instruction simulated. Newer simulators reduce the expansion factor to about 10, by saving and reusing translations of individual instructions. This paper describes an experimental simulator which takes the progression one step further, translating groups of instructions as a unit. This approach, combined with flow analysis, reduces the expansion factor to about 4. The new simulator simulates System/370 on a RISC, namely the IBM RT PC.