Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
IRSIM: an incremental MOS switch-level simulator
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Introduction to algorithms
Certified timing verification and the transition delay of a logic circuit
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Algebraic decision diagrams and their applications
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Symbolic functional and timing verification of transistor-level circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Computing logic-stage delays using circuit simulation and symbolic elmore analysis
Proceedings of the 38th annual Design Automation Conference
Handling special constructs in symbolic simulation
Proceedings of the 39th annual Design Automation Conference
Formal Methods in System Design
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We recently introduced symbolic timing simulation (STS) using data-dependent delays as a tool for verifying the timing of full-custom transistor-level circuit designs, and for the functional verification of delay-dependent logic. While STS leverages efficient symbolic encodings to yield huge gains over conventional simulation methodologies, it still suffers from a problem known as event multiplication. We discuss this problem and present an event-list management technique based on event-clusters, and a new simulator which utilizes this technique. Finally, we demonstrate substantial speedups on a wide range of test cases, including exponential improvement on a simple logic chain.