Efficient ray tracing of volume data
ACM Transactions on Graphics (TOG)
Fast volume rendering using a shear-warp factorization of the viewing transformation
SIGGRAPH '94 Proceedings of the 21st annual conference on Computer graphics and interactive techniques
Accelerated volume rendering and tomographic reconstruction using texture mapping hardware
VVS '94 Proceedings of the 1994 symposium on Volume visualization
EM-Cube: an architecture for low-cost real-time volume rendering
HWWS '97 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Vizard II, a PCI-card for real-time volume rendering
HWWS '98 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
The VolumePro real-time ray-casting system
Proceedings of the 26th annual conference on Computer graphics and interactive techniques
High-Quality Splatting on Rectilinear Grids with Efficient Culling of Occluded Voxels
IEEE Transactions on Visualization and Computer Graphics
Ray Casting Architectures for Volume Visualization
IEEE Transactions on Visualization and Computer Graphics
Architectures for real-time volume rendering
Architectures for real-time volume rendering
Dependency graph scheduling in a volumetric ray tracing architecture
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware
Real-time visualization of large volume datasets on standard PC hardware
Computer Methods and Programs in Biomedicine
A compact shader for FPGA-based volume rendering accelerators
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
Efficient space leaping for ray casting architectures
VG'01 Proceedings of the 2001 Eurographics conference on Volume Graphics
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In this paper, we present the RACE II Engine, which uses a hybrid volume rendering methodology that combines algorithmic and hardware acceleration to maximize ray casting performance relative the total amount of volume memory throughput contained in the system. The challenge for future volume rendering accelerators will be the ability to process higher resolution datasets at over 10Hz without utilizing large-scale, and therefore, expensive designs. The limiting performance factor for large datasets will be the throughput between the volume memory subsystem and computational units. Unfortunately, the throughput between memory devices and computational units does not scale with Moore's law. As a result, memory efficient solutions are needed that maximize the input-output relationship between volume memory throughput and frame rate. The RACE II design utilizes this approach and achieves an input-output relationship of up to 4 × larger than many solutions proposed in literature. As a result, this architecture is well suited for meeting the challenges of next generation datasets.