A rapid modeling technique for measurable improvements in factory performance
Proceedings of the 30th conference on Winter simulation
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An analysis of tool capabilities in the photolithography area of an ASIC fab
Proceedings of the 39th conference on Winter simulation: 40 years! The best is yet to come
Analysis of multiple process flows in an ASIC fab with a detailed photolithography area model
Proceedings of the 40th Conference on Winter Simulation
A heuristic load balancing scheduling method for dedicated machine constraint
IEA/AIE'06 Proceedings of the 19th international conference on Advances in Applied Artificial Intelligence: industrial, Engineering and Other Applications of Applied Intelligent Systems
Single toolset modeling approaches in semiconductor manufacturing
Proceedings of the Winter Simulation Conference
Proceedings of the Winter Simulation Conference
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In this paper we present the results of a simulation study for the solution of load-balancing problems in a semiconductor wafer fabrication facility. In the bottleneck area of photolithography the steppers form several different subgroups. These subgroups differ, for example, in the size of the masks that have to be used for processing lots on the steppers of a single group. During lot release it is necessary to distribute the lots over the different stepper groups in such a way that global targets like cycle time minimization, the maximization of the number of finished lots and due date performance are inside a certain range. We present a simulation model of a wafer fab that models the photolithography area in a detailed manner. By means of this simulation model it is possible to decide at release time on which stepper subgroup processing of the lots of a certain product is favorable.