Graph algorithms and NP-completeness
Graph algorithms and NP-completeness
Computer
The Wisconsin multicube: a new large-scale cache-coherent multiprocessor
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Efficient parallel algorithms for testing k-connectivity and finding disjoint s-t paths in graphs
SIAM Journal on Computing
Reliable computer systems (2nd ed.): design and evaluation
Reliable computer systems (2nd ed.): design and evaluation
Fault-Tolerance Analysis of One-Sided Crosspoint Switching Networks
IEEE Transactions on Computers
Wavelength Division Multiple Access Channel Hypercube Processor Interconnection
IEEE Transactions on Computers
Parallel supercomputing in MIMD architectures
Parallel supercomputing in MIMD architectures
Multiprocessor system architectures
Multiprocessor system architectures
Graph Algorithms
Advanced Computer Architecture: Parallelism,Scalability,Programmability
Advanced Computer Architecture: Parallelism,Scalability,Programmability
Graphs and Hypergraphs
Families of Optimal Fault-Tolerant Multiple-Bus Networks
IEEE Transactions on Parallel and Distributed Systems
Computing in the RAIN: A Reliable Array of Independent Nodes
IEEE Transactions on Parallel and Distributed Systems
Survivable Computer Networks in the Presence of Partitioning
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Tolerant Switched Local Area Networks
IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium
A Proxy-Network Based Overlay Topology Resistant to DoS Attacks and Partitioning
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 16 - Volume 17
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We present an efficient approach to characterizing the fault tolerance of multiprocessor systems that employ multiple shared buses for interprocessor communication. Of concern is connective fault tolerance, which is defined as the ability to maintain communication between any two fault-free processors in the presence of faulty processors, buses, or processor-bus links. We introduce a model called processor-bus-link (PBL) graphs to represent a multiple-bus system's interconnection structure. The model is more general than previously proposed models, and has the advantages of simple representation, broad application, and the ability to model partial bus failures. The PBL graph implies a set of component adjacency graphs that highlights various connectivity features of the system. Using these graphs, we propose a method for analyzing the maximum number of faults a multiple-bus system can tolerate, and for identifying every minimum set of faulty components that disconnects the processors of the system. We also analyze the connective fault tolerance of several proposed multiple-bus systems to illustrate the application of our method.