The architecture of a programmable systolic chip
Advances in VLSI and Computer Systems
Communications of the ACM - Special section on computer architecture
The warp computer: Architecture, implementation, and performance
IEEE Transactions on Computers
ACM Computing Surveys (CSUR)
Warp: an integrated solution of high-speed parallel computing
Proceedings of the 1988 ACM/IEEE conference on Supercomputing
Towards dataflow analysis of communicating finite state machines
Proceedings of the eighth annual ACM Symposium on Principles of distributed computing
Data flow analysis of communicating finite state machines
ACM Transactions on Programming Languages and Systems (TOPLAS)
The NuMesh: a modular, scalable communications substrate
ICS '93 Proceedings of the 7th international conference on Supercomputing
A New Theory of Deadlock-Free Adaptive Routing in Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
Supporting systolic and memory communication in iWarp
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
A Theory of Deadlock-Free Adaptive Multicast Routing in Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
A Necessary and Sufficient Condition for Deadlock-Free Adaptive Routing in Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
A Necessary and Sufficient Condition for Deadlock-Free Adaptive Routing in Wormhole Networks
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
Deadlock-freeness of hexagonal systolic arrays
Information Processing Letters
Hardware support for multithreaded execution of loops with limited parallelism
PCI'05 Proceedings of the 10th Panhellenic conference on Advances in Informatics
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Under the systolic communication model, each cell (or processor) in a parallel processing system can operate directly on data residing at the cell's input queues and move computed results directly to the cell's output queues. Incoming and outgoing messages need not be stored in the cell's local memory, if not required by the computation. By avoiding these local memory accesses, systolic communication can achieve high efficiency when executing many systolic algorithms. Though efficient, systolic communication may lead to deadlocks at run time if data arriving at a cell's input queues are improperly ordered. This paper describes the nature of this deadlock problem, gives an abstract formulation of the problem, and provides a deadlock avoidance strategy.