Principles of a computer immune system
NSPW '97 Proceedings of the 1997 workshop on New security paradigms
Fundamentals of Digital Logic with VERILOG Design
Fundamentals of Digital Logic with VERILOG Design
MUXTREE Revisited: Embryonics as a Reconfiguration Strategy in Fault-Tolerant Processor Arrays
ICES '98 Proceedings of the Second International Conference on Evolvable Systems: From Biology to Hardware
Embryonics + Immunotronics: A Bio-Inspired Approach to Fault Tolerance
EH '00 Proceedings of the 2nd NASA/DoD workshop on Evolvable Hardware
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A phylogenetic, ontogenetic, and epigenetic view of bio-inspired hardware systems
IEEE Transactions on Evolutionary Computation
QoS-LI: QoS loss inference in disadvantaged networks -- part II
Proceedings of the 11th communications and networking simulation symposium
Virtualization within a parallel array of homogeneous processing units
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
The use of very deep submicron technology makes VLSI-based digital systems more susceptible to transient or soft errors, and thus compromises their reliability. This paper proposes an architecture inspired by the human immune system that allows tolerance of such errors. An error in a digital system designed using the proposed architecture is treated as an antigen by the system. Using its distributed defense mechanism the system heals itself from the effect of the error. A major advantage of this architecture is that, the outputs of functional cells are connected to the inputs of other physically adjacent functional cells without having to go through complicated routing.