Distributed Systems for System Architects
Distributed Systems for System Architects
An Architecture for Self-Healing Digital Systems
Journal of Electronic Testing: Theory and Applications
Reconfigurable Architecture for Autonomous Self-Repair
IEEE Design & Test
Column-Based Precompiled Configuration Techniques for FPGA
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor
DSN '07 Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Online fault tolerance for FPGA logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of RSIC Test Sequence Based on ALFSR Generation Circuit
ISISE '08 Proceedings of the 2008 International Symposium on Information Science and Engieering - Volume 01
The use of triple-modular redundancy to improve computer reliability
IBM Journal of Research and Development
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Self-repair ability of a toroidal and non-toroidal cellular developmental model
ECAL'05 Proceedings of the 8th European conference on Advances in Artificial Life
On the practicality of using intrinsic reconfiguration for fault recovery
IEEE Transactions on Evolutionary Computation
Fault Tolerance Using Dynamic Reconfiguration on the POEtic Tissue
IEEE Transactions on Evolutionary Computation
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Self-repairing digital systems have received increasing attention as modern systems are getting more complex and fast. Currently available self-repairing architectures have, however, some limitations such as storage overhead required to prepare all possible rewiring strategies and temporal incorrectness caused by elongated repairing time. In this paper, we propose a novel self-repairing architecture for fast fault recovery with an efficient use of limited resources, which can be easily applied to real complex digital systems. The proposed architecture consists of three layers: a working layer, a control layer, and an interface layer. The working layer employs a hybrid scheme of using both redundant and empty cells with a newly devised self-test. This relieves the overhead of redundant cells required to be prepared in advance by considering every possible fault situation. In the control layer, an ordered assignment control is proposed. The order of working-priority of each processor that controls a normal cell in the working layer is predetermined. A faulty processor is detected by a majority decision among neighboring control processors and corrected by rearranging the order of working-priority. The interface layer connects an external PC for reprogramming. Through this fault recovery mechanism, the system can keep normal functioning under noisy environments. We implemented the proposed self-repairing architecture using an field-programmable gate array board with an application of a dot-matrix LED display and verified its robust operation. The proposed architecture can be widely used as a new platform for self-repairing systems.