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Exploiting a new level of DLP in multimedia applications
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High Performance Compilers for Parallel Computing
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Cross-Loop Reuse Analysis and Its Application to Cache Optimizations
LCPC '96 Proceedings of the 9th International Workshop on Languages and Compilers for Parallel Computing
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EDTC '97 Proceedings of the 1997 European conference on Design and Test
Torrent Architecture Manual
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LCTES '05 Proceedings of the 2005 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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CC'07 Proceedings of the 16th international conference on Compiler construction
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Science of Computer Programming
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The Single Instruction Multiple Data (SIMD) model for finegrained parallelism was recently extended to support SIMD operations on disjoint vector elements. In this paper we demonstrate how SIMdD (SIMD on disjoint data) supports e#ective vectorization of digital signal processing (DSP) benchmarks, by facilitating data reorganization and reuse. In particular we show that this model can be adopted by a compiler to achieve nearoptimal performance for important classes of kernels.