Path Delay Estimation using Power Supply Transient Signals: A Comparative Study using Fourier and Wavelet Analysis

  • Authors:
  • Abhishek Singh;Jitin Tharian;Jim Plusquellic

  • Affiliations:
  • University of Maryland, Baltimore;University of Maryland, Baltimore;University of Maryland, Baltimore

  • Venue:
  • Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
  • Year:
  • 2003

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Abstract

Transient Signal Analysis (TSA) is a parametric device testingtechnique based on the analysis of dynamic (transient) current(i{DDT}) drawn by the core logic from the power supply pads in aCMOS digital circuit. In previous work, we develop a test procedurethat can be used both to detect signal variations caused bydefects and to obtain delay information in defect free chips. Phasespectra of transient signals obtained using discrete Fourier transformare shown to track path delays of defect-free chips under awide range of process variations. However, in recent work, wewere able to demonstrate through simulation experiments incorporatingdeep submicron transistor models, a circuit design andpath sensitization scenario in which our existing TSA method isnot able to yield accurate predictions of path delays. More specifically,a circuit composed of two inverter chains constructed withwidely varying transistor sizes was shown to produce path delaysthat were weakly correlated across a set of worst case processmodels. In this paper, an alternative wavelet-based analysis ofi{DDT} waveforms is shown to improve the accuracy of predictingmultiple path delays under these conditions.