Scheduling and dispatching: some issues of the critical ratio dispatch rule in semiconductor manufacturing

Authors:
Oliver Rose
Affiliations:
University of Würzburg, Würzburg, Germany
Venue:
Proceedings of the 34th conference on Winter simulation: exploring new frontiers
Year:
2002

Citing 2
Cited 8

WIP evolution of a semiconductor factory after a bottleneck workcenter breakdown

Proceedings of the 30th conference on Winter simulation
Modeling methodology: the shortest processing time first (SPTF) dispatch rule and some variants in semiconductor manufacturing

Proceedings of the 33nd conference on Winter simulation

Factory scheduling and dispatching: accelerating products under due-date oriented dispatching rules in semiconductor manufacturing

Proceedings of the 35th conference on Winter simulation: driving innovation
Analysis of production control methods for semiconductor research and development fabs using simulation

WSC '05 Proceedings of the 37th conference on Winter simulation
Economy of scale effects for large wafer fabs

Proceedings of the 38th conference on Winter simulation
Indirect cycle-time quantile estimation for non-FIFO dispatching policies

Proceedings of the 38th conference on Winter simulation
A bottleneck detection and dynamic dispatching strategy for semiconductor wafer fabrication facilities

Winter Simulation Conference
Rule-based scheduling in wafer fabrication with due date-based objectives

Computers and Operations Research
Development and introduction of a combined dispatching policy at a high-mix low-volume ASIC facility

Proceedings of the Winter Simulation Conference
A detailed model for a high-mix low-volume asic fab

Proceedings of the Winter Simulation Conference

Quantified Score

Hi-index	0.01

Visualization

Abstract

In this paper, we examine the cycle time and on-time delivery performance of a semiconductor wafer fabrication facility (wafer fab) under critical ratio (CR) dispatch regime. It turns out that determining appropriate due dates for this rule is a critical task. We provide a detailed analysis of the wafer fab behavior for a large range of due date values. From the results of the experiments we develop a heuristic for conservative due date estimates.