OBBTree: a hierarchical structure for rapid interference detection
SIGGRAPH '96 Proceedings of the 23rd annual conference on Computer graphics and interactive techniques
Collision Detection for Interactive Graphics Applications
IEEE Transactions on Visualization and Computer Graphics
Rapid Collision Detection by Dynamically Aligned DOP-Trees
VRAIS '98 Proceedings of the Virtual Reality Annual International Symposium
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware
Space-efficient FPGA-accelerated collision detection for virtual prototyping
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
ReChannel: Describing and simulating reconfigurable hardware in systemC
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fast ray-triangle intersection computation using reconfigurable hardware
MIRAGE'07 Proceedings of the 3rd international conference on Computer vision/computer graphics collaboration techniques
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We present a hardware architecture for a single-chip acceleration of an efficient hierarchical collision detection algorithm as well as simulation results for collision queries using this architecture. The architecture consists of two main stages, one for traversing simultaneously a hierarchy of discretely oriented polytopes, and one for intersecting triangles. Within each stage, the architecture is deeply pipelined and parallelized. For the first stage, we compare and evaluate different traversal schemes for bounding volume hierarchies. A simulation in VHDL shows that a hardware implementation can offer a speed-up over a software implementation by orders of magnitude. Thus, real-time collision detection of complex objects at rates required by force-feedback and physically-based simulations can be achieved.