Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
DCT-Domain Embedded Memory Compression for Hybrid Video Coders
Journal of VLSI Signal Processing Systems - Special issue on recent advances in the design and implementation of signal processing systems
HW-SW Co-Design and Verification of a Multi-Standard Video and Image Codec
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
A 27 mW 1.1 mm2 Motion Estimator for Picture-Rate Up-converter
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
IC for motion-compensated de-interlacing, noise reduction, and picture-rate conversion
IEEE Transactions on Consumer Electronics
IEEE Transactions on Consumer Electronics
Trend and Challenge on System-on-a-Chip Designs
Journal of Signal Processing Systems
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The importance of low-power design is not just critical to portable devices but also to line powered equipment like TV products. Power dissipation strongly influences the price of the chip, since the packaging and cooling costs increase dramatically with increasing power dissipation. In this work, we analyze and optimize algorithm and architecture of a picture rate up-conversion module. We perform algorithm/architecture co-design in which we meet high quality specification while keeping the power dissipation low. In the algorithm front, we focus on the motion estimation which is computationally the most intensive part of the picture-rate up-conversion application. We analyze the following parameters of the motion estimation algorithm: The number of motion estimation iterations per input image pair and the image scanning order of individual iterations. Further, we apply novel pre-processing technique to address the issue of reducing the already extremely low number of motion vector candidate evaluations. However, optimal selection of motion vector candidates is a necessity to achieve high picture quality. In the architectural front, to cope with the large memory bandwidth requirements of the application, we use multi-level caching to exploit locality of reference. Further, we apply data compression to the image data stored in memory, to reduce the memory capacity and bandwidth requirements. Both the above techniques significantly reduce the overall power dissipation.